The present invention is directed to a lead frame, and a manufacturing method therefor, with minimal susceptibility to metal diffusion and cracking.
Lead frames come in a variety of forms and are generally used to mount semiconductor chips. FIG. 1 is a diagram of a general lead frame.
FIG. 1 shows lead frame 10, including coined portion 11, pad portion 12, and outer lead 13. Coined portion 11 and pad portion 12 are usually silver-plated. Outer lead 13, on the other hand, is generally solder-plated using a tin (Sn)-lead (Pb) alloy to enhance its solderability after resin-molding in the semiconductor package process.
Resin-molded products undergo a wet treatment for the solder plating. The wet treatment deteriorates the reliability of the products considerably. Accordingly, to solve this problem, a plate layer of the lead frame is coated to withstand the wet treatment before beginning the semiconductor package process.
FIG. 2 is a sectional view of lead frame 20 that has undergone the above coating process. Lead frame 20 contains a copper (Cu) substrate 21 coated with a nickel (Ni) layer 22. The Ni layer 22 is coated with a palladium (Pd)--Ni alloy layer 23, which, in turn, is coated with a Pd layer 24.
The Ni layer 22 acts as a barrier layer to the diffusion of Cu molecules in order to prevent the Cu molecules from diffusing to the outermost surface of lead frame 20 and thereby generating a Cu compound such as a sulfide. If the thickness of the Ni layer 22 is less than 400 micro-inches, however, the Cu molecules diffuse through the porosities existing in the Ni layer 22. If the thickness of the Ni layer 22 is more than 400 micro-inches, the Ni layer 22 cracks when lead frame 20 is bent.
FIG. 3 is a sectional view of lead frame 30 that has been developed to prevent diffusion of Cu molecules through the porosities. FIG. 3 uses similar reference numerals to those used in FIG. 2 to designate layers that are shown in FIG. 2.
Lead frame 30 includes Cu substrate 21, coated with a Ni strike layer 25 having a thickness of approximately 5 micro-inches. The Ni strike layer 25 is coated with a Pd--Ni alloy layer 23 having a thickness of approximately 3 micro-inches. Despite this structure, lead frame 30 cannot prevent discoloration of the lead frame surface and deterioration of solderability, because a Cu compound, such as an oxide or a sulfide, is still generated at the outermost surface of lead frame 30.
FIG. 4 is a sectional view of lead frame 40 with an enhanced structure. FIG. 4 uses similar reference numerals to those used in FIGS. 2 and 3 to designate layers that are also shown in FIGS. 2 or 3.
Lead frame 40 includes a gold (Au) strike layer 26 acting as an adhesive layer between a Ni layer 22 and a Pd--Ni alloy layer 23 to bond the two layers together. The Pd--Ni alloy layer 23 is coated with a Pd layer 24 for trapping Ni molecules diffusing from the Pd--Ni alloy layer 23. The Pd layer 24 is coated with an Au layer 27 to reduce porosities and enhance solderability and wire bonding.
In each of the above-described conventional methods, an intermediate layer is formed of Ni or a Pd--Ni alloy to prevent Cu molecules of the substrate from diffusing outward. However, Ni molecules diffuse from the intermediate layer with the Cu molecules. As a result, Ni or an Ni compound, such as Ni oxide, is generated at the outermost surface of the lead frame due to diffusion of Ni molecules. This hampers solderability more severely than Cu or a Cu compound. For example, when Ni of approximately 5% exists at the outermost surface of the lead frame, solderability is remarkably decreased. In addition, Ni oxide cannot be easily removed by surface washing.
Accordingly, it is desirable to plate a surface of a lead frame with only Pd. However, this tends to be expensive and the adhesiveness of Pd is low.
Japanese Patent Laid-Open Gazette No. 6-112389 to Hitachi Co. discloses a Pd plating method by which the surface of the lead frame is heat-treated and a diffusion double layer is formed on a Pd interface to enhance its adhesiveness. The heat-treating required in the above plating method, however, lowers productivity and causes a surface of the lead frame to become oxidized, thereby deteriorating solderability and wire bonding.
Moreover, if the total thickness of the plated layer is approximately 100 to 1,000 micro-inches, problems arise in the semiconductor package process. For example, when bending the lead during trimming and forming of the outer lead, structural defects, such as cracks in an intermediate layer and separation of the layers, result. Moreover, because the cracks increase in proportion to the thickness of the plated layer, there is a limit as to how much the thickness of the plated layer can be increased.
In addition, the closer the plated layer of the lead frame comes to the outer lead portion from the pad, the thicker the plated layer becomes. As the thickness of the plated layer increases, the variation in the thickness with respect to each portion of the lead frame increases. Accordingly, it is difficult to control the desired thickness of the plating.
In multi-layered plating, the above-described problems are severe, resulting in a decrease in production and an increase in production costs.